`timescale 1ns / 1ps
/******************************************************************************
*                                                                             *
* UTICA softcore v0.1                                                         *
*                                                                             *
* Copyright (c) 2012 Andrew D. Zonenberg                                      *
* All rights reserved.                                                        *
*                                                                             *
* Redistribution and use in source and binary forms, with or without modifi-  *
* cation, are permitted provided that the following conditions are met:       *
*                                                                             *
*    * Redistributions of source code must retain the above copyright notice  *
*      this list of conditions and the following disclaimer.                  *
*                                                                             *
*    * Redistributions in binary form must reproduce the above copyright      *
*      notice, this list of conditions and the following disclaimer in the    *
*      documentation and/or other materials provided with the distribution.   *
*                                                                             *
*    * Neither the name of the author nor the names of any contributors may be*
*      used to endorse or promote products derived from this software without *
*      specific prior written permission.                                     *
*                                                                             *
* THIS SOFTWARE IS PROVIDED BY THE AUTHORS "AS IS" AND ANY EXPRESS OR IMPLIED *
* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF        *
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN     *
* NO EVENT SHALL THE AUTHORS BE HELD LIABLE FOR ANY DIRECT, INDIRECT,         *
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT    *
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,   *
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY       *
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT         *
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF    *
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.           *
*                                                                             *
******************************************************************************/

/**
	@file CoreClockManagement.v
	@author Andrew D. Zonenberg
	@brief Clock management PLL and BUFG's
 */
module CoreClockManagement(
	clk_20mhz,
	clk_20mhz_ibufg, clk_ddr_p, clk_ddr_n, clk_mcb_calib, clk_ddr_p_raw, clk_ddr_n_raw, clk,
	main_clk_pll_reset, main_clk_pll_locked
    );
	
	////////////////////////////////////////////////////////////////////////////////////////////////
	// IO declarations
	input wire clk_20mhz;
	
	output wire clk_20mhz_ibufg;
	output wire clk_ddr_p;
	output wire clk_ddr_n;	
	output wire clk_ddr_p_raw;
	output wire clk_ddr_n_raw;
	output wire clk_mcb_calib;
	output wire clk;
	
	input wire main_clk_pll_reset;
	output wire main_clk_pll_locked;
	
	////////////////////////////////////////////////////////////////////////////////////////////////
	// The fun stuff goes here
	
	wire clk_feedback;
	
	//Raw stuff before bufgs
	wire clk_raw;
	wire clk_mcb_calib_raw;
	
	//Global clock buffers
	IBUFG bufg_clk_20mhz(.I(clk_20mhz), .O(clk_20mhz_ibufg));
	BUFG bufg_ddr_p		(.I(clk_ddr_p_raw),		.O(clk_ddr_p));
	BUFG bufg_ddr_n		(.I(clk_ddr_n_raw),		.O(clk_ddr_n));
	BUFG bufg_clk  		(.I(clk_raw),    			.O(clk));
	BUFG bufg_mcb_calib	(.I(clk_mcb_calib_raw), .O(clk_mcb_calib));
	
	PLL_ADV #
	(
		.BANDWIDTH          ("OPTIMIZED"),
		.CLKIN1_PERIOD      (50000),						//20 MHz board clock
		.CLKIN2_PERIOD      (50000),
		.CLKFBOUT_MULT      (24),							//20*24 = 480 MHz VCO frequency
		.CLKOUT0_DIVIDE     (3),							//160 MHz DDR clock
		.CLKOUT1_DIVIDE     (3),							//160 MHz DDR clock
		.CLKOUT2_DIVIDE     (6),							//80 MHz system clock
		.CLKOUT3_DIVIDE     (12),							//40 MHz calibration clock
		.CLKOUT4_DIVIDE     (1),							//unused output
		.CLKOUT5_DIVIDE     (1),							//unused output
		.CLKOUT0_PHASE      (0.000),
		.CLKOUT1_PHASE      (180.000),
		.CLKOUT2_PHASE      (0.000),
		.CLKOUT3_PHASE      (0.000),
		.CLKOUT4_PHASE      (0.000),
		.CLKOUT5_PHASE      (0.000),
		.CLKOUT0_DUTY_CYCLE (0.500),
		.CLKOUT1_DUTY_CYCLE (0.500),
		.CLKOUT2_DUTY_CYCLE (0.500),
		.CLKOUT3_DUTY_CYCLE (0.500),
		.CLKOUT4_DUTY_CYCLE (0.500),
		.CLKOUT5_DUTY_CYCLE (0.500),
		.SIM_DEVICE         ("SPARTAN6"),
		.COMPENSATION       ("INTERNAL"),
		.DIVCLK_DIVIDE      (1),							//No pre-divider
		.CLKFBOUT_PHASE     (0.0),
		.REF_JITTER         (0.005000)
	)
	main_clk_pll
	(
		.CLKFBIN     (clk_feedback),
		.CLKINSEL    (1'b1),
		.CLKIN1      (clk_20mhz_ibufg),
		.CLKIN2      (1'b0),
		.DADDR       (5'b0),
		.DCLK        (1'b0),
		.DEN         (1'b0),
		.DI          (16'b0),
		.DWE         (1'b0),
		.REL         (1'b0),
		.RST         (main_clk_pll_reset),
		.CLKFBDCM    (),
		.CLKFBOUT    (clk_feedback),
		.CLKOUTDCM0  (),
		.CLKOUTDCM1  (),
		.CLKOUTDCM2  (),
		.CLKOUTDCM3  (),
		.CLKOUTDCM4  (),
		.CLKOUTDCM5  (),
		.CLKOUT0     (clk_ddr_p_raw),
		.CLKOUT1     (clk_ddr_n_raw),
		.CLKOUT2     (clk_raw),
		.CLKOUT3     (clk_mcb_calib_raw),
		.CLKOUT4     (),
		.CLKOUT5     (),
		.DO          (),
		.DRDY        (),
		.LOCKED      (main_clk_pll_locked)
	);


endmodule
